Recently, high integration and fineness have been promoted in a device process, and the integrity of a device active region in a surface layer and the improvement of gettering ability to capture impurities such as metals caused by increase of bulk micro defects (BMD) formed by oxide precipitates in a bulk have been required of a silicon wafer.
In response to these requirements, various approaches have been attempted. For example, in order to eliminate defects (mainly grown-in defects) on a wafer surface, it has been performed that a wafer obtained by the Czochralski method (CZ method) is subjected to a high temperature heat treatment (annealing) in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes. In this high temperature annealing, the reason why the temperature of the high temperature annealing is 1100° C. or more is to effectively eliminate defects, and by setting the temperature at 1350° C. or less, problems such as deformation and metal contamination of a wafer can be prevented.
However, in the case that a silicon wafer having a diameter of 200 mm or more is subjected to the high temperature annealing as described above, slip dislocations, which penetrate a wafer from its back side to the front, are remarkably generated, and they have been detected by a visual inspection and a particle counter.
It is known that such slip dislocations are generated mainly due to the weight of a wafer itself, and there is a tendency that as the diameter of the wafer is more increased, these slip dislocations is easy to be generated. Namely, as compared to the case that a silicon wafer having a diameter of 200 mm is subjected to a high temperature annealing, when a silicon wafer having a large diameter of 300 mm or more is subjected to a high temperature annealing, the generation of slip dislocations are remarkably increased, and it is extremely difficult to prevent the generation. Such slip dislocations are further grown in a device process, they cause a failure in a device process, and they have been one of factors of lowering a yield.
Also, in general, when a high temperature annealing is performed, a wafer supporting jig (boat) has been used for supporting a wafer and a three-point or four-point supporting jig has been usually used. However, when a wafer is supported by a four-point supporting boat, a stress applied to each one of four points must be less than that applied to each one of three points in theory. However, in fact, seen from a tendency of the generation of slip dislocations in an annealed wafer, slip dislocations are generated from three out of four points. From this fact, it is found that stresses are not applied uniformly to four points when a wafer is suppressed, and a wafer is supported mainly by three out of four points, i.e., stresses are applied non-uniformly to a wafer. On the other hand, when a wafer is supported by using a three-point supporting boat, since stresses are applied uniformly to three point, the stresses are more dispersed as compared to the four-point supporting boat, but slip dislocations are generated in the annealed wafer subjected to a high temperature annealing.
As a method of suppressing such slip dislocations, a method of optimizing a temperature increasing rate or the like has been generally known. However, by optimizing a temperature increasing rate, the temperature increasing rate becomes slow, which is substantially equal to the extension of the annealing time at a high temperature, and thus, this can not be a fundamental solution for suppressing slip dislocations. Moreover, the time required for an annealing process is prolonged, and, as a result, it has caused the deterioration of the productivity.